VLSI Implementation of Vedic Squarer – Verilog Code

Hello Friends, Last Week I wrote a post sharing the Verilog Codes of the Project titled “VLSI Implementation of Vedic Multiplier”. Continuing the same research area further, In this post I want to share with you my Verilog code for High speed squarer using Vedic Mathematics technique.

This Squarer Architecture is based on the “Duplex” technique of Vedic Mathematics. The Verilog code for the above architecture for 4bit binary number can be downloaded from the link given below:

The code has been organized in the following manner:

  1. Sub-modules for each type of duplex has been prepared separately
    • Duplex for 1 bit
    • Duplex for 2 bit
    • Duplex for 3 bit and
    • Duplex for 4 bit.
  2. In the beginning, the code calculates all the duplexes and then the carry is forwarded to the subsequent bit starting from the LSB to MSB.
  3. While writing the code for each of the duplex modules, I found whatever the input be, the output of the Duplex is always confined within 2 bits. That’s the reason, the output in each of the module is always “sum” and “carry” indicating 2 variables each of single bit.
  4. While the algorithm has been correctly programmed, it is found that it gives slight wrong answer at the last possible input at “4’b1111” i.e. 15. Though reasons are unknown to me, I would love to hear from you the possible correction.

I hope this code will assist the knowledge thirsty students and researchers in their quest for research. If you have any suggestions or query, you can comment below.

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