# VLSI Implementation of Vedic Multipliers – Verilog Code

Hello friends! I am posting on this blog after a very long time.

When I was in School, I studied Vedic Mathematics which is used for faster mental calculations. Later during my undergraduate project days, I came across binary multipliers which forms the backbone of the modern day processors especially Digital Signal Processors.

When I was in School, I studied Vedic Mathematics which is used for faster mental calculations. Later during my undergraduate project days, I came across binary multipliers which forms the backbone of the modern day processors especially Digital Signal Processors.

High speed multipliers forms the basis of many Digital Signal Processing applications like Image Processing, Speech Processing, Video Processing, etc. Multipliers are basic building blocks of functions like transforms, filtering, etc.

Meanwhile, when I was working on this multiplier thing, I came across many research papers citing the use of Vedic Multiplication technique for Design and Implementation of Multipliers for high speed multiplication.

In this post, I want to share with you, my Verilog code which I had written for the implementation of multipliers using Vedic Multiplication technique.

In this post, I want to share with you the code for 4x4 (i.e. 4 bit by 4bit) multiplier Verilog code using

Meanwhile, when I was working on this multiplier thing, I came across many research papers citing the use of Vedic Multiplication technique for Design and Implementation of Multipliers for high speed multiplication.

In this post, I want to share with you, my Verilog code which I had written for the implementation of multipliers using Vedic Multiplication technique.

In this post, I want to share with you the code for 4x4 (i.e. 4 bit by 4bit) multiplier Verilog code using

*technique of Vedic Mathematics.***Urdhava Tiryakbhyam (Vertically and crosswise)**
Download the Source Code Here : [ DropBox Download Link ]

You can find the RTL Schematic of the vedic multiplier in the below given image.

RTL Schematic of the Vedic Multiplier as seen in Xilinx ISE |

Please note that this is just the implementation of the multiplier based on Vedic multiplication technique. I am not sure about its speed compared to the conventional multipliers like Braun, Baugh-Wooley, etc.

When I used to work in my University, I used to check the delay, power, area and other performance parameters using the “Cadence RTL Compiler” software for which my University holds a valid organizational license. But currently being an Individual, I am not in possession of the software and hence not in position to calculate the performance parameters.

If you are willing you can suggest any alternative software or can calculate the parameters and post it here as comment.

I hope this post will help out many students or researchers who are working in the Binary Multipliers or VLSI Implementation of Vedic mathematics area.

When I used to work in my University, I used to check the delay, power, area and other performance parameters using the “Cadence RTL Compiler” software for which my University holds a valid organizational license. But currently being an Individual, I am not in possession of the software and hence not in position to calculate the performance parameters.

If you are willing you can suggest any alternative software or can calculate the parameters and post it here as comment.

I hope this post will help out many students or researchers who are working in the Binary Multipliers or VLSI Implementation of Vedic mathematics area.

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